RTL-SADE: A High-Level Tool for the Specification of ASICs in Data-Flow Type Applications

A method and tool for logic design with data-flow and state-transition diagrams is presented. The method is based on object-oriented characterization and encapsulation of the control and timing requirements of combinational and sequential data-path units. The method makes it possible to use CASE (computer-aided software engineering) methods based on system-level semantics in conjunction with current register-transfer-level VHDL and logic synthesis tools. The timing model for data-flow diagrams is based on causality, which makes it possible to automatically schedule data-path operations in data-flow oriented applications, such as DSP and telecommunications ASIC design. The tool, called RTL-SADE, automatically generates VHDL models for logic synthesis programs from graphical specifications.